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ICs for Communications
High Voltage Subscriber Line IC HV-SLIC PEB/F 4065 Version 3.0
Data Sheet 03.98 DS 1
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PEB/F 4065 Revision History: Previous Version: Page (in previous Version) Page (in current Version) Current Version: 03.98 01.96 Subjects (major changes since last revision)
SLICOFI(R) is a registered trademark of SIEMENS AG. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http:/ /www.siemens.de/Semiconductor/address/address.htm.
Edition 03.98 Published by Siemens AG, HL SP, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB/F 4065
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 3
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 AC-Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Semiconductor Group
3
1998-03-01
High Voltage Subscriber Line IC HV-SLIC
PEB/F 4065
Version 1.1 1 Overview
SPT
The High Voltage Subscriber Line IC PEB 4065 is a rugged and reliable interface between the telephone line and the SLICOFI, a low voltage Subscriber Line Interface and Codec Filter IC. It is fabricated in a Smart Power Technology offering a breakthrough voltage of at least 170 V. P-DSO-20-5 The PEB 4065 provides battery feeding between - 24 V and - 80 V and internal ringing injection with a differential ring voltage up to 85 Vrms. In order to achieve these high amplitudes an auxiliary positive battery voltage is used during ringing. This voltage can also be applied in order to drive very long telephone lines. The SLIC is designed for a voltage feeding - current sensing line interface concept and provides sensing of transversal and longitudinal current on both wires. A power-down mode offers reduced power consumption at full functionality; in the power denial mode the device is switched off turning the line outputs to a high impedance state. 1.1 * * * * * * Features
High voltage line feeding Internal ring and metering signal injection Sensing of transversal and longitudinal line current Reliable 170 V Smart Power Technology Battery voltage - 24 V ... - 80 V Boosted battery mode for long telephone lines and up to 85 Vrms balanced ringing * Polarity reversal * Small P-DSO-20-5 power package
Type PEB/F 4065
Semiconductor Group
Ordering Code on request
4
Package P-DSO-20-5
1998-03-01
PEB/F 4065
Overview 1.2 Functional Description
VH
BGND
Supply Switch
RING
a
Vab
VHINT
Buffer Differential I/V-Converter Buffer
Control
C1 C2
V/I Converter
V2W
TIP
b
Reference
PDN
Current sensor
VBAT Supply
T
L
VBAT
VBIM
AGND VSS VDD
ITB10371
Figure 1
Block Diagram
The PEB 4065 supports AC and DC control loops based on feeding a voltage Vab to the line and sensing the transversal line current Iab (Figure 2). It converts a unipolar input voltage V2W into a differential output voltage Vab with an AC receiving gain of Gr = VabAC/V2WAC = 40. This is accomplished by converting the input voltage to a current which is used to transpose the low voltage signals of the interface to the high voltage line feeding section. This current is reconverted to two voltages of opposite phase which are referenced to the positive and negative supply voltage, respectively. Thus the differential DC line-voltage in all normal polarity modes except ringing is related to the input voltage by
VabDC = VBAT - VHINT + Vfix - 40 x V2WDC VBAT negative battery voltage VHINT internal positive supply voltage Vfix internal voltage drop of supply filter (appr. 2 V). Depending on the operation mode, VHINT is switched either to VH (VHINT = VH - 1 V) or to
BGND (VHINT = - 0.5 V) via the supply switch.
Semiconductor Group
5
1998-03-01
PEB/F 4065
Overview Controlled by C2, the polarity of Vab can be reversed and the DC-line-voltage then is
VabDC = - (VBAT - VHINT + Vfix - 40 x V2WDC).
The transversal and longitudinal currents are measured in the buffers and scaled images are provided at the IT and IL pin, respectively:
IT = (Ia + Ib)/100 = Iab/50
IL = - (Ia - Ib)/100 = - ILong/50.
The PEB 4065 operates in four modes controlled by ternary logic signals at the C1 and C2 input. Additionally, in the active modes a polarity reversal of the output voltage can be programmed (see Table 1). Power down (PD): Power consumption is reduced by decreasing bias current levels. All functions operate at some small performance reductions. In this mode each of the line outputs can be programmed to show high impedance. HI b switches off the TIP buffer, while the current through the RING output still can be measured by IT or IL. Programming HI a reverses the polarity and switches off the RING buffer. Conversation (CONV): This is the regular transmit and receive mode for voiceband and teletax. The line driving section is operated between VBAT and BGND. Boosted battery (BB): In order to drive longer telephone lines an auxiliary positive battery voltage VH is used, enabling a higher DC-voltage across the line. Ringing (RING): This mode also uses the auxiliary voltage VH in order to provide a balanced ring signal of up to 85 Vrms. The ring tone without any DC-component has to be switched to the V2W input. Internally a DC-voltage is superimposed. This voltage is proportional to the total supply voltage VH - VBAT and amounts to typically 23 V at VH - VBAT = 120 V. The current sensing functions are available for ring trip detection. The Power Denial (PDN) state is intended to reduce power consumption of the linecard to a minimum: the PEB 4065 is switched off completely by connecting the PDN pin to VDD, no operation is available. With respect to the output impedance of TIP and RING two PDN-modes have to be distinguished. A resistive one (PDNR) provides a connection of 15 k each from TIP to BGND and RING to VBAT, respectively, while the outputs of the buffers show high impedance (Figure 3). The other mode (PDNH) offers high impedance at TIP and RING. It is entered when, in addition to connecting PDN to VDD, the programming inputs C1, C2 are tied to VIL. All other combinations of C1, C2 yield the resistive power denial state PDNR.
Semiconductor Group 6 1998-03-01
PEB/F 4065
Overview Table 1 Programming of Operation Modes C2 (Pin 13)
VIL
C1 (Pin 12)
VIZ
RING NP BB NP CONV NP
VIH
HI a RP HI b NP PD NP
VIL VIZ VIH
RING RP BB RP CONV RP
RP...Reverse Polarity
NP HI a RP HI b NP
Normal Polarity
Ring wire set to high impedance Tip wire set to high impedance
Buffer
Long a
RING
ZL 2
Vab
ab
Buffer
ZL 2
~ ~
b ab = ( a + b ) /2 Long = ( a - b ) /2
TIP
Long
ITS10372
Figure 2
Definition of Output Current Directions
Semiconductor Group
7
1998-03-01
PEB/F 4065
Overview
BGND
PDNH
PDNR
HIZ
R TG 15 k
TIP
HIZ RING
R RB 15 k
PDNH PDNR
VBAT
ITS10373
Figure 3
TIP and RING Impedance in Power Denial
Semiconductor Group
8
1998-03-01
PEB/F 4065
Overview 1.3 Pin Description P-DSO-20-5 (11 mm)
V BAT V SS L T AGND C2 C1 AGND PDN V BAT
20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10
ITP10374
V BAT RING TIP N.C. VH BGND V DD V 2W V BIM V BAT
Due to reverse bending of the leads, the numbering of the pins is also reversed.
Figure 4 Table 2 Pin No.
Pin Configuration (top view) Pin Definition and Functions Symbol Type Function Input (I) Output (O) Supply O Negative battery supply voltage (- 24 ... - 80 V), referred to BGND Subscriber loop connection, negative wire in normal polarity; direction of positive Ia current out of this pin Subscriber loop connection, more positive wire in normal polarity; direction of positive Ib current into this pin Not connected Auxiliary positive battery supply voltage (0 ... + 90 V) used in ringing and boosted battery mode Battery ground: TIP, RING, VBAT and VH refer to this pin Positive supply voltage (+ 5 V), referred to AGND
9 1998-03-01
1, 10, 11, VBAT 20 2 RING
3
TIP
O
4 5
-
N.C. Supply
VH
6 7
BGND
Supply Supply
VDD
Semiconductor Group
PEB/F 4065
Overview Table 2 Pin No. Pin Definition and Functions (cont'd) Symbol Type Function Input (I) Output (O) I Two wire input voltage; multiplied by + 20 and - 20, respectively, it appears at the TIP and RING outputs Down scaled image of the total supply voltage (VHINT - VBAT); scaling factor 40 Power denial, reference output when connected to ground via a resistor, switches the device off when connected to VDD Analog ground: VDD, VSS and all signal and control pins with exception of TIP and RING refer to AGND Ternary logic input, controlling the operation mode; in case of thermal overload this pin sinks a current of typ. 550 A Ternary logic input, controlling the operation mode Current output representing the transversal current scaled down by 50; In normal polarity this pin sinks the IT current. Current output representing the longitudinal current scaled down by 50; For Ilong flowing out of TIP and RING this pin sinks the IL current. Negative supply voltage (- 5 V), referred to AGND
8
V2W
9 12
VBIM
PDN
O I/O
13, 16 14
AGND C1
Supply I/O
15 17
C2
I O
IT
18
IL
O
19
VSS
Supply
Semiconductor Group
10
1998-03-01
PEB/F 4065
Electrical Characteristics 2 2.1 Table 3 Parameter Battery voltage Auxiliary supply voltage Symbol Limit Values min. max. 0.5 90 160 170 5.5 0.4 0.5 150 V V V V V V V C referred to BGND referred to BGND - - referred to AGND referred to AGND - - - - - - - - Human body model - 90 - 0.5 - - Unit Condition Electrical Characteristics Absolute Maximum Ratings
VBAT VH
Total battery supply VH - VBAT voltage, continuously
VH - VBAT Total battery supply voltage, pulse < 1 ms VDD supply voltage VSS supply voltage
Ground voltage difference Input voltages Voltages on current outputs Voltages on PDN RING, TIP voltages, continuously RING, TIP voltages, pulse < 1 ms1) RING, TIP voltages, 1) pulse < 1 s
VDD - 0.4 VSS - 5.5 VBGND - VAGND - 0.5
-
Junction temperature Tj
V2W, VC1, VC2 VIT, VIL VPDN Va, Vb Va, Vb Va, Vb
VSS - 0.3
- 3.5 - 0.3
VDD + 0.3 V VDD + 0.3 V
VDD + 0.3 V VBAT - 0.3 VH + 0.3 V VBAT - 10 VH + 10 VBAT - 30 VH + 30
- 1 V V kV
ESD-voltage, all pins -
1)
See Test Figure 10.
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
11
1998-03-01
PEB/F 4065
Electrical Characteristics 2.2 Table 4 Parameter Battery voltage Auxiliary supply voltage Total battery supply voltage Symbol Limit Values min. max. - 24 85 150 5.25 - 4.75 0.3 70 85 3 + 3.2 0 V V V V V V C C V V V referred to BGND referred to BGND - referred to AGND referred to AGND - PEB 4065 PEF 4065 - RING CONV, PD, BB - 80 5 - 4.75 - 5.25 - 0.3 0 - 40 -3 - 3.2 - 3.2 Unit Condition Operating Range
VDD supply voltage VSS supply voltage
Ground voltage difference Ambient temperature Voltage compliance IT, IL Input range V2W
VBAT VH VH - VBAT VDD VSS
-
Tamb VIT, VIL V2W
Note: In the operating range the functions given in the circuit description are fulfilled.
2.3 Table 5 Parameter Junction to case Junction to ambient Symbol Limit Values 5 20 Unit K/W K/W Condition - with heatsink, typ. Thermal Resistances
Rth, jC Rth, jA
Semiconductor Group
12
1998-03-01
PEB/F 4065
Electrical Characteristics 2.4 Electrical Parameters
Min/max values are valid within the full operating range. If PEB- and PEF-specifications are different, both values can be found in the respective column. Testing is performed according to the test figures with external circuitry as depicted in Figure 4. Unless otherwise stated, load impedance RL = 600 . Test temperatures are 25 and 70 C for PEB, - 40, 25 and 85 C for PEF-type (without heatsink). DC line voltages refer to VBAT = - 70 V and VH = + 60 V. Table 6 No. Supply Currents and Power Dissipation Symbol Mode Limit Values min. typ. Power Denial 1. 2. 3. 4. max. PEB/PEF 120/150 120/150 250/300 30 120 10 Unit Test Fig.
Parameter
VDD current VSS current VBAT current VH current
IDD ISS IBAT IH
PDNH, PDNR PDNH PDNR PDNH PDNR PDNH, PDNR PD PD PD PD PD
- - - -
50 50 150 10 50 1
A A A A
1 1 1 1
Power Down 5. 6. 7. 8. 9.
V2W = - 0.5 V1) IDD ISS IBAT IH PQ
- - - - - 0.5 0.3 3.3 1 - 1.0 0.4 4.3/4.4 10 315 mA mA mA A
1 1 1 1
VDD current VSS current VBAT current VH current
Quiescent power dissipation
mW 1
Conversation, Normal and Reverse Polarity 10. 11. 12. 13. 14.
V2W = - 0.5 V1)
- - - - - 0.8 0.4 4.0 1 - 1.0/1.1 0.5/0.6 5.8/5.9 10 420 mA mA mA A
1 1 1 1
VDD current VSS current VBAT current VH current
Quiescent power dissipation
IDD ISS IBAT IH PQ
CONV CONV CONV CONV CONV
mW 1
Semiconductor Group
13
1998-03-01
PEB/F 4065
Electrical Characteristics Table 6 No. Supply Currents and Power Dissipation (cont'd) Symbol Mode Limit Values min. typ. Boosted Battery Mode Normal and Reverse Polarity 15. 16. 17. 18. 19. max. PEB/PEF 1.0 2.0 6.1/6.2 4.8 740 Unit Test Fig.
Parameter
V2W = - 0.5 V1)
mA mA mA mA
1 1 1 1
VDD current VSS current VBAT current VH current
Quiescent power dissipation
IDD ISS IBAT IH PQ
BB BB BB BB BB
- - - - -
0.8 1.7 4.0 3.0 -
mW 1
Ringing Mode Normal and Reverse Polarity 20. 21. 22. 23. 24.
1)
V2W = 0 V
- - - - - 2.3 2.8 8.8 7.1 2.6 3.2 12/12.5 10 mA mA mA mA
1 1 1 1
VDD current VSS current VBAT current VH current
Quiescent power dissipation
IDD ISS IBAT IH PQ
RING RING RING RING RING
1300 1500
mW 1
IBAT and IH depend on the value of V2W: IBAT (V2W) = IBAT(0) + |V2W|/440 typ. (PD, CONV, BB) IH (V2W) = IH(0) + |V2W|/440 typ. (BB)
Semiconductor Group
14
1998-03-01
PEB/F 4065
Electrical Characteristics Table 7 DC-Characteristics
Symbol Mode Limit Values min. PEB/ PEF Line Termination TIP, RING 25. Power down DC line voltage 26. 27. Conversation |Vab,DC| DC line voltage 28. 29. 30. Ringing DC line voltage 31. Output current limit |Vab,DC| |Ia,max|, |Ib,max| |Vab,DC| PD 46 49 52 V 2 typ. max. PEB/ PEF Unit Test Test Condition Fig.
No. Parameter
V2W = - 0.5 V
PD
- 14
- 11 66.5
-8 68.5
V V 2
V2W = - 2 V V2W = 0 V
CONV 65
CONV 46.6 CONV - 14 RING 22.1
47.8
48.8
V
V2W = - 0.5 V
- 12.2 - 10.4 V 25 - - 15 27.7 130 130/ 135 V mA mA 2 3
V2W = - 2 V V2W = 0 V V2W = - 0.5 V Va, Vb acc. to
Test Figure 3 9
PD 85/80 others 90/85 PDNR 12/11
RTG 32. Loop open resistance TIP to BGND RRB 33. Loop open resistance RING to VBAT
34. Power denial ILeak,a output leakage current 35. 36. High impedance output leakage current 37.
18/19 k
Ib = 2 mA
PDNR 12/11
15
18/19 k
Ia = 2 mA
PDNH - 30
-
30
A
-
VBAT < Va < VH
ILeak,b ILeak,a
HI a
- 30 - 30
- -
30 30
A A -
VBAT < Va < VH VBAT < Va < VH-3
Ileak,b
HI b
- 30
-
30
A
VBAT < Vb < VH-3
Semiconductor Group
15
1998-03-01
PEB/F 4065
Electrical Characteristics Table 7 DC-Characteristics (cont'd)
Symbol Mode Limit Values min. PEB/ PEF Reference Voltage Outputs PDN, VBIM 38. Output voltage on PDN typ. max. PEB/ PEF 1.35 Unit Test Test Condition Fig.
No. Parameter
Vref
all
1.15
1.25
V
1
-
39. Battery image VBIM voltage 40. Two-wire Input V2W 41. Input current 42. Input capacitance 43. IT output current 44. 45. 46. 47. IL output current 48. 49. 50. |IL|
CONV, - 1.75 - 1.7 PD BB, RING
- 1.65 V V
1
-
- 3.25 - 3.18 - 3.1
I2W
-
all -
- 30 -
- -
30 20
A pF
- -
- 3.2 V < V2W < 3.2 V -
Current Outputs IT, IL |IT| PD, - CONV PD, 380 CONV CONV 0.95 RING PD, - CONV PD, CONV PD, 65 CONV CONV 180 - - 15 420 1.05 20 30 30 135 320 A A mA A A A A A 2 2
V2W = - 0.5 V Ia = Ib = 0 Ia = Ib = 20 mA1) Ia = Ib = 50mA1) Ia = Ib = 0 Ia = Ib = 0 Ia = Ib = 20 mA1) Ia = 15 mA, Ib = 25 mA Ia = 37.5 mA, Ib = 62.5 mA
Semiconductor Group
16
1998-03-01
PEB/F 4065
Electrical Characteristics Table 7 DC-Characteristics (cont'd)
Symbol Mode Limit Values min. PEB/ PEF Control Inputs C1, C2 51. H-input voltage 52. Z-input voltage 53. L-input voltage 54. Input leakage current 55. Thermal overload current C1 typ. max. PEB/ PEF - 0.8 -2 5 Unit Test Test Condition Fig.
No. Parameter
VIH VIZ VIL ILeak
all all all all
2 - 0.8 - -5
- - - -
V V V A
- - - -
- - - - 5 V < VC1(2) < + 5 V
Itherm
all
500
550
-
A
-
VC1 = - 3.2 V
Tjoff 56. Switching Temperature Tjon (guaranteed by design)
1)
all all
- -
165 145
- -
C C
- -
- -
Polarity of Ia and Ib is reversed for measurement in reverse polarity mode
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
17
1998-03-01
PEB/F 4065
Electrical Characteristics 2.5 Table 8
No. Parameter Symbol Mode min. Limit Values typ. max. PEB/ PEF Unit Test Test Condition Fig.
AC-Characteristics (Normal and reverse polarity unless otherwise stated)
Line Termination TIP, RING Receive gain 57. 58. 59. Gain flatness dGr (guaranteed by design) 60. Gain tracking dGr (guaranteed by design) 61. Total harmonic distortion Vab Teletax distortion 62. 63. THD Gr CONV, 31.92 32.04 BB CONV 31.88 32.04 CONV, - 0.05 - BB CONV - 0.2 - 32.16 32.2 0.05 dB dB dB - 4
V2W,AC = 50 mVrms f = 1015 Hz Iab = 20 mA Iab = 50 mA
300 Hz < f < 3400 Hz V2W,AC = 50 mVrms 3 dBm0 > Vab > - 20 dBm0 f = 1015 Hz
0.2
dB
-
CONV -
-
0.3
%
4
V2W,AC = 50 mVrms f = 1015 Hz Iab = 20 mA f = 16 kHz RL = 200 Iab = 50 mA Vab,AC = 2 Vrms Vab,AC = 5 Vrms Iab = 0 mA, Vab = 55 V Vab,AC = 2 Vrms Iab = 30 mA Vlong = 3 Vrms 300 Hz < f < 3.4 kHz Iab = 30 mA V2W,AC = 150 mVrms 300 Hz < f < 3.4 kHz Iab = 30 mA
THDTTX CONV
5
- -
- -
3 3
% %
64. 65. Psophometric NP, Vab noise 66. Longitudinal LTRR to transversal rejection ratio Vlong/Vab TLRR 67. Transversal to longitudinal rejection ratio Vab/Vlong
- CONV -
- -
5 - 75 -
% dBmp 4 dB 6
CONV 61/58 -
CONV 50
-
-
dB
7
Semiconductor Group
18
1998-03-01
PEB/F 4065
Electrical Characteristics Table 8 (cont'd)
Symbol Mode min. Limit Values typ. max. PEB/ PEF Unit Test Test Condition Fig.
No. Parameter
Power supply PSRR rejection ratio 68. VBAT/Vab CONV, 33 40 BB PD 30/28 - BB 33/30 40 50 50 25 - - - - - - - dB dB dB dB dB dB
4
300 Hz < f < 3.4 kHz VSupply,AC = 100 mVp Iab = 30 mA
69. VH/Vab 70. VDD/Vab 71. VSS/Vab 72. Ringing voltage
CONV, 33 BB CONV, 33 BB
VRING
RING
67
Vrms, 8 diff
RL = 1 k CL = 1 F f = 66 Hz V2W = 1.7 Vrms VH = 80 V f = 20 Hz V2W = 2.2 Vrms f = 66 Hz V2W = 1.7 Vrms V2W = 50 mVrms f = 1015 Hz Iab = 20 mA Iab = 50 mA
73. Ringing voltage with extended VH 74. Ringing distortion Transversal current ratio 75. 76. 77. Gain flatness dGit (guaranteed by design) 78. Gain tracking dGit (guaranteed by design) 79. Total harmonic distortion VIT THD, IT THD RING
84
-
-
Vrms, 8 diff % 8
-
-
4
Transversal Current Output IT Git CONV, 33.89 33.98 BB CONV 33.89 33.98 CONV, - 0.05 - BB CONV - 0.2 - 34.07 34.07 0.05 dB dB dB - 4
300 Hz < f < 3400 Hz V2W,AC = 50 mVrms Iab = 20 mA 3 dBm0 > Vab > - 20 dBm0 f = 1015 Hz V2W,AC = 50 mVrms f = 1015 Hz Iab = 15 mA
0.2
dB
-
CONV -
0.01
0.3
%
4
Semiconductor Group
19
1998-03-01
PEB/F 4065
Electrical Characteristics Table 8 (cont'd)
Symbol Mode min. Limit Values typ. max. PEB/ PEF - 100 -97 Unit Test Test Condition Fig.
No. Parameter
80. Psophometric NP, VIT noise Frequency response VIT/V2W (guaranteed by design) 81. Amplitude 82. Phase Longitudinal LITRR to transversal current output rejection ratio Vlong/VIT 83. 84. Power supply PSRR rejection ratio 85. VBAT/VIT 86. VH/VIT 87. VDD/VIT 88. VSS/VIT -
CONV - CONV
-
dBmp 4 4
Iab = 30 mA, T>00C
-400Cf = 200 kHz V2W,AC = 50 mVrms ILine = 20 mA Cs = 0.2 nF
- 0.5 100 CONV
1.7 -
1.95 -
dB deg 6
Vlong = 3 Vrms Iab = 30 mA
75 81
- -
- -
dB dB 4
300 Hz < f < 3.4 kHz
f = 1015 Hz
300 Hz < f < 3.4 kHz Vsupply,AC = 100 mVp Iab = 30 mA
CONV, 50 PD BB 50 CONV 50 CONV 50
60 60 60 60
- - - -
dB dB dB dB
Semiconductor Group
20
1998-03-01
PEB/F 4065
Electrical Characteristics Table 9 External Elements in the Application Circuit (Figure 5) Typical values are used in the test circuits, unless otherwise specified. Typ. Value Tolerance 25 k - - Limit Values min. max. 50 k power dissipation increases with smaller R1 clipping for IT x R 2 > 3 V or IL x R3 > 3 V - Comment
Ext. Part Function
R1
Biasing, current reference
R2 , R3
IT, IL gain
adjustment
1 k
0.1% (rel.) -
-
RS
Protection, isolation of capacitive load Protection C for the internal supply voltage filter
50
0.1% (rel.) 30
-
R5 , R6 C1
50
0.1% (rel.) - 10 nF
- -
-
20% 22 F (f3dB 3 Hz)
f3dB increases with smaller C1,
causing worse low frequency PSRR from VBAT
CS
Suppression 15 nF of voltage spikes, frequency compensation
5% (rel.)
200 pF 20 nF
-
C2, C3
VDD, VSS
supply voltage blocking
1 F
20%
10 nF
-
C4 C5
VH blocking
100 nF
-
-
-
C2, C3 > 1 F and C4 C5 allows arbitrary switching sequence of all supply voltages incl.
ground
VBAT blocking 100 nF
20%
100 nF -
Note: Exceeding the min./max. limits can cause stability problems!
Semiconductor Group
21
1998-03-01
PEB/F 4065
Electrical Characteristics
5 V -5 V
60 V -70 V
PEB 3065 SLICOFI 5V 14 C1 15 C2
7 19 VDD VSS
5 VH
C2 1 F C3 1 F C4 100 nF C5 100 nF 1, 10, 11, 20 VBAT
TIP 3
1)
Subscriber Line
RS
30
R5 CS 15 nF CS 15 nF
51 b
R1
24.9 k
8V 2W 12 PDN
PEB 4065
RING 2 30 BGND AGND VBIM 6 13 16 9 2) C1 22 F/10 V
1)
RS
R6
51 a
T T 17 18
R IT 1 k
1) 2)
R IL 1 k
Careful symmetrical board layout with respect to a and b Connect close to pin 16
Figure 5
Application Circuit
Semiconductor Group
22
+
ITS10506
1998-03-01
PEB/F 4065
Electrical Characteristics
V DD
PDN
VBIM VSS C BIM V DD V BAT VH
SS
DD
BAT
H
R PDN VREF
VBIM
PDN
VSS
V DD
V BAT
VH
TIP RING
PEB 4065
BGND
V2W
C1 C2
L
R IL
T
AGND
R IT
See Testcond.
ITS10507
Test Figure 1
DC Characteristics and Power Dissipation
Semiconductor Group
23
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS C BIM VBIM
25 k PDN
V DD
V BAT
VH
VSS
V DD
V BAT
VH RING Vab
TIP
a b
PEB 4065
BGND
V2W
C1 C2
L L
AGND T
T
ITS10508
See Testcond.
Test Figure 2
DC Line Voltage and Currents
Semiconductor Group
24
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS C BIM VBIM
25 k PDN
V DD
V BAT
VH
VSS
V DD
V BAT
VH RING
TIP
a, max b, max
Va Vb
PEB 4065
BGND
V2W
C1 C2
L
R IL
AGND T
R IT Va , Vb : BGND / VBAT in PDN, CONV BGND in BB, RING
ITS10509
See Testcond.
Test Figure 3
Output Current Limit
DC and AC
VSS C BIM VBIM
25 k PDN
V DD
V BAT
VH
VSS
V DD
V BAT
VH
TIP
RS RS RL Vab, AC
RING
V2W, AC V2W, DC V2W
C1
PEB 4065
BGND AGND
C2
L
R IL
T
R IT
VIT, AC
ITS10510
Gr =
Vab, AC V2W, AC Vab, AC 1000 VIT, AC 660
See Testcond.
G IT =
Test Figure 4
Receive Gain, Transversal Current Ratio, THD, Noise and Power Supply Rejection
25 1998-03-01
Semiconductor Group
PEB/F 4065
Electrical Characteristics
VSS C BIM VBIM
25 k PDN
V DD
V BAT
VH
VSS
V DD
V BAT
VH
TIP 2 F RING
RS RS RL Vab, AC
V2W, AC V2W, DC V2W
C1
PEB 4065
BGND AGND T
C2
L
R IL
R IT
ITS10511
See Testcond.
Test Figure 5
Teletax Distortion
VSS C BIM VBIM VSS V DD V BAT VH
TIP PDN RING
V DD
V BAT
VH
RS RS
R L/2 VLong R L/2
25 k
~ ~
Vab, AC
PEB 4065
V2W, DC V2W
C1 C2 BGND AGND T
L
R IL
R IT
V IT
ITS10512
See Testcond.
Test Figure 6
Longitudinal to Transversal Rejection Ratio
Semiconductor Group
26
1998-03-01
PEB/F 4065
Electrical Characteristics
VSS C BIM VBIM
25 k PDN
V DD
V BAT
VH
VSS
V DD
V BAT
VH
TIP
RS RS
R L/2 R L/2
VLong, AC Vab, AC
RING
V2W, AC V2W, DC V2W
C1
PEB 4065
BGND AGND T
C2
L
R IL
R IT
ITS10513
See Testcond.
Test Figure 7
Transversal to Longitudinal Rejection Ratio
VSS C BIM VBIM
25 k PDN RING
V DD
V BAT
VH
VSS
V DD
V BAT
VH
RS
TIP
CL RS RL VRING
PEB 4065
V2W V2W
C1 C2 BGND
L
R IL
AGND T
R IT
ITS10514
See Testcond.
Test Figure 8
Ringing
Semiconductor Group
27
1998-03-01
PEB/F 4065
Electrical Characteristics
V DD
PDN
VSS C BIM VBIM
PDN
V DD
V BAT
VH
SS
VSS
DD
V DD
BAT
V BAT
H
VH
TIP RING
R PDN
b a
V TIP V BAT
PEB 4065
BGND
VRING VBAT
V2W
C1 C2
L
R IL
AGND T
R IT
ITS10515
See Testcond.
Test Figure 9
Output Resistance in PDNR Mode
V DD
PDN
VBIM VSS C BIM V DD V BAT VH
SS
VSS
DD
V DD
BAT
V BAT
H
VH
TIP 30 30 RING
R PDN VREF
VBIM
PDN
VH +10 V / 1 ms VH +20 V / 1 s VBAT -10 V / 1 ms VBAT -20 V / 1 s
PEB 4065
BGND
V2W
C1 C2
L
R IL
AGND T
R IT
ITS10516
Test Figure 10
TIP, RING Overvoltage Pulses
Semiconductor Group
28
1998-03-01
PEB/F 4065
Package Outlines 3 Package Outlines P-DSO-20-5 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 29
Dimensions in mm 1998-03-01
GPS05755

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